
Joining two (or more) pcbs

When attempting to merge two boards using cut and paste the resulting
design rarely maintains consistency between the board and schematic.
The main reason for this would appear to be the way eagle renames components/nets when there are duplicates names.  My understanding of this is that the elements are renamed in the order they are added to the sch/brd. There is obviously going to be some inconsistency when pasting a board file and then pasting individual sheets.


The work around to avoid this is to ensure that all components and nets
in the designs of interest have unique identifiers.

Step 1. renumber the boards such that there are no common designators.
The ULP cmd_renumber_2, is a modified version of the standard ULP that comes with the Eagle installation, with the addition of an option to start the renumbering at any value the user specifies.
e.g. board 1 start from 1, board 2 start from 101, etc. 

Step 2. Rename all the nets.
Run the ULP renamesig_3 in the board window.  This ulp is a brute force renaming of the nets by adding a suffix to the netname.

NOTE that for steps 1 and 2 both sch and brd windows must be open.

You should now have 2 designs with no common component or net names.

Step 3. Cut and paste 
Let us call the two boards pcb_1 and pcb_2
Open the board to be added, pcb_2 say, group everything  in the brd window and cut.  It is advisable to turn on all layers so that nothing is missed.
Open pcb_1, but open only the brd window, this will allow the pcb_2 brd to be pasted in. 
save pcb_1 and open pcb_2 schematic, cut sheet 1 then open pcb_1 sch and paste
Repeat with other sheets as necessary.

Now with pcb_1 brd and sch open run the ERC and hopefully everything should be consistent.

A few nets will need to be renamed to tidy up the design, primarily the
power and gnd nets that should be common , but this is relatively
trivial.

NOTE it is of course advisable to save and rename the designs you are working on to ensure that the originals are not corrupted/loose consistency if anything goes wrong.  The usual disclaimers apply and you do all this at your own risk of course.:-)
If you experience problems/ no consistency the main check to make is that all components and nets really do have unique names in the relevant designs before starting stage 3. This can be don by exporting a BOM from the board and the netlist from the sch.


